Dr. Adrian Slowik

Anschrift:: Adrian Slowik
Universität Paderborn
Institut für Informatik
Fakultät für Elektrotechnik,
Informatik und Mathematik
Fürstenallee 11
33102 Paderborn
Deutschland

Raum: F2.303
Tel.: +49 5251 60-6681
Fax: +49 5251 60-6697
e-mail: adrian@uni-paderborn.de

First of August 2002, I joined the research group of Prof. Kastens at the University of Paderborn to participate in the design of a flexible network processor. Since then, I am a member of the GigaNetIC project, which aims to design and evaluate a powerful and flexible network processor architecture, as well as a supporting toolset. Besides other tools, this toolset includes a C-compiler and a domain specific compiler for packet processing. Yoy can download a paper that describes activities related to the GigaNetIC project being conducted in Paderborn here: A Holistic Methodology for Network Processor Design.

Here is a list of GigaNetIC-related publications I have been involved in:

BSSer: Peter Bleckmann, Gunnar Schomaker, und Adrian Slowik. Virtualization with Prefetching Abilities based on iSCSI. In Proceedings of the International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI 2004), Nice, France, September 2004 (accepted paper).
HNP+04: Gunnar Hagen, Jörg-Christian Niemann, Mario Porrmann, Christian Sauer, Adrian Slowik, und Michael Thies. Developing an IP-DSLAM Benchmark for Network Processor Units. In ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004), Munich - Germany, 19 - 23 Juni 2004.
GKL+04: Matthias Grünewald, U. Kastens, Dinh Khoi Le, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert, Michael Thies, und Adrian Slowik. Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. In PARELEC 2004, International Conference on Parallel Computing in Electrical Engineering, Dresden, Germany, 2004.
KLST04: Uwe Kastens, Dinh Khoi Le, Adrian Slowik, und Michael Thies. Feedback Driven Instruction-Set Extension. In Proceedings of ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, D.C., USA, Juni 2004.

My personal interests are in the design and implementation of tools for packet classification and packet processing tasks. Currently, I am one of the driving forces behind c-ment, a development environment for packet classification and packet processing. So far, this system consists of a packet classification language similar to Solidum's pax (now IDT), a packet processing language, and a graphical user interface. A more detailed outline of this subproject can be found here.

I receveived my diploma in computer science in 1993, and a PhD in computer science in 1999, both from the University of Paderborn. You can download a pdf of my PhD Thesis here: "Loop and Data Transformations for Cache-Coherent Parallel Processors". From December 1999 up to July 2002, I was an employee at avodaq AG. During that time I have been on the road as a consultant and Cisco certified instructor (CCSI) in the area of networking, especially network management and network security.

My previous research interests have been loop and data transformations for the automatic parallelization of nested loop programs. I developed some optimization techniques for cache memories. During that time, I was especially interested in programming languages for parallel computing, e.g., High Performance Fortran (HPF), and compilation techniques for distributed memory machines. And last but not least, I like Java: Point your browser to this link and experience some very early Java examples.